Alif Semiconductor /AE722F80F55D5AS_CM55_HP_View /CANFD /CANFD_MEM_STAT

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Interpret as CANFD_MEM_STAT

7 43 0 0 00 0 0 0 0 0 0 0 0 (Val_0x0)ACFA 0 (Val_0x0)TXS 0 (Val_0x0)TXB 0 (Val_0x0)HELOC

HELOC=Val_0x0, TXB=Val_0x0, TXS=Val_0x0, ACFA=Val_0x0

Description

Memory Status Register

Fields

ACFA

Acceptance Filter Accept. If the CANFD_MEM_PROT[MDEIF] or CANFD_MEM_PROT[MAEIF] bit is set because of an error in the address range of the ACF, this bit is set. Then acceptance filtering is disabled and all frames will be accepted. The ACFA bit can be reset similar to an interrupt flag by writing a 0x1 to it. But because it will be set while the reception is still active, it is required to reset if later after the reception has been completed and the CANFD_RTIF[RIF] bit has been set. This bit is also reset if the CANFD_CFG_STAT[RESET] = 0x1.

0 (Val_0x0): Normal operation of ACF

1 (Val_0x1): ACF disabled: all received frames are accepted

TXS

Transmission Stop. If the CANFD_MEM_PROT[MDEIF] or CANFD_MEM_PROT[MAEIF] bit is set because of an error while the priority reordering machine accesses the memory, then any new transmission is stopped. If there is an active transmission, this will be completed before the stop, but if an error occurs during this transmission then no retransmission will be started. The TXS bit is reset if the CANFD_CFG_STAT[RESET] = 0x1.

0 (Val_0x0): Normal operation

1 (Val_0x1): Transmission stopped

TXB

Transmission Block. If the CANFD_MEM_PROT[MDEIF] or CANFD_MEM_PROT[MAEIF] bit is set because of an error while the CAN protocol machine is reading data for transmission, then the transmission is immediately blocked. If the CANFD_SRCFG[SREIF] bit is set, then the transmission is immediately blocked too. The TXB bit is reset if the CANFD_CFG_STAT[RESET] = 0x1.

0 (Val_0x0): Normal operation

1 (Val_0x1): Transmission blocked

HELOC

Host Side Memory Error Location. This bit field will be updated with every new error during a read access from the host side. This is sufficient, because read errors during read accesses from the CAN side will be signaled by the ACFA, TXS and TXB bits. The HELOC bit field will only be updated in case of an error, but not in case of a warning caused by a corrected single bit error.

0 (Val_0x0): No error during access from host side

1 (Val_0x1): Error during access from host side in TBUF

2 (Val_0x2): Error during access from host side in RBUF

3 (Val_0x3): Error during access from host side in ACF

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